1. Field of the Invention
The invention described herein is related to fault isolation in microelectronic circuitry. More specifically, the present invention is directed to locating circuit defects in integrated circuits by comparing images of the magnetic field thereof with those of standard reference integrated circuit known to be free from the defect.
2. Description of the Prior Art
As integrated circuitry becomes increasingly compact and the packaging associated therewith becomes more complex, the localization of circuit defects becomes correspondingly difficult. The localization of flaws is particularly difficult for those classified to the high resistance (HR) defect class of packaging and interconnect anomalies causing an increase in the impedance of a signal line to beyond the designed specification thereof. These HR defects include cracked signal traces, cracked plated through-holes, delaminated vias and improperly wetted controlled collapse chip connection (C4) bumps. Such HR defects can result in devices that do not operate at optimum speed, have an increased probability of failing in the field, or simply do not work at all.
The physical size of microelectronic circuitry presents unique failure analysis challenges. In some cases, microscopic dissection of a failed circuit may yield the location of the undesired anomaly. However, the failed circuit is destroyed by the process, thus precluding any subsequent functional testing should the inspiration to do so suddenly befall the tester.
The prevailing non-destructive method for localizing HR defects in integrated circuits is time domain reflectometry (TDR). The TDR technique involves applying a current pulse of short duration to an input port of a signal line of an integrated circuit and monitoring the input port for one or more reflections of the applied pulse. The time measured between the application of the pulse and the detection of the reflected signal is an indication of the distance from the input port to the location of the impedance change. However, such reflected signals may be due to normal transitions within the device and not necessarily due to an undesired anomaly. Thus, tedious analysis by comparison to reflection characteristics of a standard device must be conducted once the data are collected. Additionally, even when the analysis is performed flawlessly, the spatial resolution of TDR in microelectronic circuitry is typically 200 microns, which is greater than the size of most components of modern integrated circuits.
It is thus apparent from the shortcomings of the prior art that the need exists for a non-destructive fault isolation technique for use in microelectronic circuitry implementing less tedious analysis while simultaneously providing higher spatial resolution.